The present invention relates to field effect transistors including a heterojunction for a channel region, and more particularly relates to countermeasures against variation in threshold voltage of a field effect transistor.
In recent years, portable communication terminals represented by cellular phones are widely used. Such portable terminals are generally driven by batteries and it is strongly desired to reduce power consumption without sacrificing operation speed in portable terminals in order to prolong the lifetime of batteries. To achieve a portable communication terminal with low power consumption without reducing operation speed, it is effective to increase drain saturation current to maintain current driveability while lowering threshold voltage to reduce supply voltage in the portable terminal. To satisfy such demands, there have been many studies on heterojunction MOS transistors (which will be hereinafter called xe2x80x9chetero MOSxe2x80x9d) using as a channel region a material with high-mobility carriers.
In a known MOS transistor, carriers travel along the interface between a gate oxide film and a silicon substrate. Energy level largely fluctuates around the interface between the gate oxide film that is an amorphous layer and the silicon substrate that is a crystal layer. Because of the energy level fluctuation, carriers are easily affected by interface scattering in the known MOS transistor, resulting in problems such as reduction of carrier mobility and increase in noise.
On the other hand, in the hetero MOS, which is a MOS transistor including a semiconductor heterojunction for a channel region, a semiconductor heterojunction interface is formed at a depth with a small distance apart from the gate insulating film of a semiconductor substrate. A channel is formed at the semiconductor heterojunction interface and carriers travel along the channel. The semiconductor heterojunction interface is an interface where crystal layers are joined together, and thus energy level at the interface does not fluctuate widely. Therefore, the influence of interface scattering on carriers is small. Accordingly, the hetero MOS has a great current driveability and an excellent characteristic of reduction in noise. Furthermore, the hetero MOS has another characteristic that its threshold voltage can be lower than that of the known MOS transistor.
Problems to be Solved
However, in the hetero MOS including a heterojunction for a channel region, the channel region is embedded and therefore threshold voltage largely depends on the thickness of an Si cap region.
FIG. 15 illustrates the structure of a known hetero MOS.
As shown in FIG. 15, the known hetero MOS 100 includes an Si substrate 101, a gate insulating film 102 formed on the Si substrate 101, a gate electrode 103 which is formed of polysilicon containing a p-type impurity of high concentration on the gate insulating film 102, and a sidewall spacer 104 which is formed on the gate insulating film 102 to cover side faces of the gate electrode 103. The Si substrate 101 includes p-type source and drain regions 105 and 106 which are formed on both sides of the gate electrode, an n-type Si cap region 107 formed in a region located between the source and drain regions 105 and 106, an n-type SiGe channel region 108 formed under the Si cap region, 107 an n-type Si buffer region 109 formed under the SiGe channel region 108, and an n-type Si body region 110 formed under the Si buffer region 109.
FIG. 16 shows the results obtained from simulations of dependency of threshold voltage on the thickness of the Si cap region 107 in the known hetero MOS 100.
As shown in FIG. 16, as the thickness of the Si cap region 107 is increased, the absolute value for its threshold voltage remarkably increases. In other words, the threshold voltage is remarkably increased. This is because as the position at which the channel is formed (i.e., the interface between the Si cap region 107 and the SiGe channel region 108) is located a more distance apart from the gate electrode, i.e., further in depth, the potential at the channel changes less enough according to the gate voltage.
In terms of processing, however, the thickness of the Si cap region 107 is reduced through fabrication processes such as an SiO2 thermal oxide film formation process and a cleaning process, and thus it is very difficult to control the thickness of the Si cap region 107. Therefore, nonuniformity in the thickness of the Si cap region 107 can be easily caused. Accordingly, variation in threshold voltage is easily caused and therefore there may be cases where a desired operation can not be performed because of increased threshold voltage.
Particularly, in an integrated circuit including a plural number of identical transistors, variation in threshold voltage among the transistors causes gaps of switching time among the transistors. As a result, the timing gaps among the transistors in the integrated circuit occur, so that the integrated circuit may not operate properly. Moreover, under consideration of variation in threshold voltage among the transistors, in order to ensure an operation margin, the latest switching timing should be set as a standard timing and therefore it is difficult to increase in operation speed of the integrated circuit.
The present invention has been contrived in order to solve the foregoing problems and an object of the present invention is to provide a semiconductor device in which an increase in threshold voltage is suppressed.
A semiconductor device according to the present invention includes: a substrate; a semiconductor layer formed in an upper part of the substrate; a gate insulating film formed on the semiconductor layer; a gate electrode formed on the gate insulating film; first source/drain regions of a first conductivity type formed on both sides of the gate electrode in the semiconductor layer, respectively; a first cap region of the first conductivity type which is formed of a first semiconductor in a region of the semiconductor layer which is located between the first source/drain regions; a first channel region which is formed under the first cap region in the semiconductor layer and formed of a second semiconductor which has a lower potential for carriers at a band edge along which the carriers travel than the corresponding potential of the first semiconductor; and a first body region of a second conductivity type which is formed of a third semiconductor under the first channel region in the semiconductor layer.
The inventive semiconductor has the structure in which the first cap region of the first conductivity type which is formed of the first semiconductor, the first channel region which is formed under the first cap region and of the second semiconductor which has a lower potential for carriers at a band edge along which the carriers travel than the corresponding potential of the first semiconductor, and the first body region of the second conductivity type which is formed of the third semiconductor under the first channel region in the semiconductor layer. Accordingly, it is possible to achieve a semiconductor device in which an increase in threshold voltage according to an increase in the thickness of the first cap region is suppressed.
The gate electrode and the first body electrode may be electrically connected to each other.
Accordingly, when a gate bias voltage is applied to the gate electrode, forward bias voltage at the same level as the gate bias voltage is applied to the first channel region via the first body region. Therefore, when the gate bias is OFF, the inventive semiconductor device is in the same state as a regular MOS transistor, whereas when the gate bias is ON, the first body region is biased in the forward direction as the gate bias voltage is increased, and thus threshold voltage is reduced. That is to say, a semiconductor device which is operable with a lower threshold voltage can be achieved. Moreover, by forming the semiconductor device in the structure in which the gate electrode and the first body region are electrically connected to each other, the amount of variation in threshold voltage according to nonuniformity in the thickness of the first cap region can be further reduced.
The inventive semiconductor device has the structure in which the cap region is depleted when a gate bias is applied thereto.
It is preferable that the concentration of an impurity of the first conductivity contained in the first cap region is 1xc3x971017 atomsxc2x7cmxe2x88x923 or more.
It is preferable that the impurity of the first conductivity type is doped into the first cap region so that at zero bias the potential at a channel which is formed at the interface between the first channel region and the first cap region changes within the range of xc2x10.05 eV according to nonuniformity in the thickness of the first cap region.
Accordingly, it is possible to achieve a semiconductor device in which variation in threshold voltage is suppressed even if nonuniformity in the thickness of the cap region occurs.
It is preferable that the concentration of an impurity of the second conductivity type contained in the first body region is 5xc3x971018 atomsxc2x7cmxe2x88x923 or more.
Accordingly, the body current generated in the lateral parasitic bipolar transistor can be suppressed and kept at a low level. Furthermore, when a voltage is applied to between the source/drain regions, a depletion layer from the source/drain regions can be prevented from expanding. Therefore, even when the concentration of the impurity in the body region is increased, the threshold voltage can be kept at a low level. As a result, the short channel effect that is caused when the gate length is shortened can be prevented.
It is preferable that the thickness of the first cap region is 10 nm or less.
The first semiconductor may be silicon.
The inventive semiconductor device may be formed in the structure in which the second semiconductor is made of silicon and at least one of germanium and carbon.
The inventive semiconductor device may further include: an additional semiconductor layer formed in an upper part of the substrate; an additional gate insulating film formed on the additional semiconductor layer; an additional gate electrode formed on the additional gate insulating film; additional first source/drain regions of the first conductivity type formed on both sides of the additional gate electrode in the additional semiconductor layer, respectively; an additional first cap region of the first conductivity type which is formed of the first semiconductor in a region of the additional semiconductor layer which is located between the additional first source/drain regions; an additional first channel region which is formed of the second semiconductor under the additional first cap region in the additional semiconductor layer; and an additional first body region of the second conductivity type which is formed of the third semiconductor under the additional first channel region in the additional semiconductor layer.
Accordingly, even if nonuniformity in the thickness of the first cap region is caused in a fabrication process or between fabrication processes, it is possible to achieve a semiconductor device in which variation in threshold voltage between transistors is suppressed.
The inventive semiconductor device may include: an additional semiconductor layer formed in an upper part of the substrate; an additional gate insulating film formed on the additional semiconductor layer; an additional gate electrode formed on the additional gate insulating film; second source/drain regions of the second conductivity type formed on both sides of the additional gate electrode in the additional semiconductor layer, respectively; a second channel region formed of a fourth semiconductor in a region of the additional semiconductor layer which is located between the second source/drain regions; and a second body region of the first conductivity type which is formed of a fifth semiconductor under the second channel region in the additional semiconductor layer, and the semiconductor device may be formed in the structure that can function as a complementary device.
It is preferable that the second channel region is of the second conductivity type.
Accordingly, variation in threshold voltage in a transistor formed on the additional semiconductor layer can be suppressed.
The gate electrode and the first body region may be electrically connected to each other and the additional gate electrode and the second body region may be electrically connected to each other.
A method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming in an upper part of a semiconductor substrate a first semiconductor layer including a first semiconductor region into which an impurity of a first conductivity type is doped and a second semiconductor region into which an impurity of a second conductivity type is doped as a complementary device; b) forming on the first semiconductor layer a second semiconductor layer and a third semiconductor layer which is formed of a semiconductor having a wider band gap than the second semiconductor layer; c) forming a mask on part of the third semiconductor layer located in the first semiconductor region, and then introducing an impurity of the first conductivity type into part of the third semiconductor located at least in the second semiconductor region, using the mask; d) removing the mask and then forming a gate insulating film and a gate electrode on part of the third semiconductor layer located in the first semiconductor region and part of the third semiconductor layer located in the second semiconductor region, respectively; and e) forming source/drain regions of the second conductivity type and source/drain regions of the first conductivity type in the first semiconductor region and in the second semiconductor region, respectively, by implanting ions of respective impurities into the first, second and third semiconductor layers using each of the gate electrodes as a mask.
According to the present invention, it is possible to achieve a semiconductor device which functions as a complementary device in which variation in threshold voltage in a hetero MIS formed in the second semiconductor region due to nonuniformity in the thickness of the third semiconductor layer that is to be the cap region can be suppressed. Furthermore, according to the present invention, no impurity of the first conductivity type is doped into the part of the third semiconductor layer which is located in the first semiconductor region. Therefore, in a semiconductor device which can be achieved according to the inventive method and functions as a complementary device, characteristics of a hetero MIS formed in the first semiconductor region are not degenerated.
It is preferable that in the step c), ions of the impurity of the first conductivity type are implanted so that the peak of the concentration profile of the impurity of the first conductivity type is in the second semiconductor layer or the third semiconductor layer.
Accordingly, variation in threshold voltage in a transistor formed in the first semiconductor region can be suppressed.